Guaranteeing that time delay changes of a timing path in a “timing safety” circuit of a circuit does not cause synchronization failure is one of the basic conditions for ensuring the circuit to work reliably. However, with manufacturing processes continuously advancing toward nano scale, the effect of variations of factors such as process, voltage, temperature (Process-Voltage-Temperature, PVT) on an integrated circuit timing gets larger and larger, and guaranteeing the timing safety becomes increasingly difficult and costly, thus making it an important research subject. In order to minimize effects on a chip timing caused by variations of factors such as PVT, it is essential to monitor PVT conditions while the chip is working, and adjust the chip according to monitored PVT information so as to guarantee that the chip timing is always correct.
In all of the factors affecting the chip timing, process variation is one of the main causes of timing fluctuation. It was said in International Technology Roadmap for Semiconductors (ITRS), 2011, that: Since the feature size is reduced, one of key problems faced by designers is that fluctuation of parameters related to a design is continuously increasing, because manufacturing parameters variations and the inherent characteristic of the atom affect channel doping. The process variation is caused by inconsistency of the manufacturing processes, being divided into global variation and local variation.
For the global variation, changes of device parameters such as oxidation layer thickness and doping concentration are the same for all transistors in the same chip. The process variations in different wafers or among chips in different batches all fall within this class. On the contrary, for the local variation (also known as mismatch or random uncorrelated variation), the effects on each transistor in the same chip are different.
The global variation describes differences of device parameters in different chips, while the device parameters in the same chip are regarded as the same. Simulation in different process corners is generally used to estimate the effect of the global variation. Each process corner is in an extreme situation, and the device parameters thereof substantially deviate from their typical values. For a fastest process corner (Fast Corner), all process fluctuations increase a drive current of the transistor, and therefore, the speed thereof is fastest. However, for a slowest process corner (Slow Corner), device speeds are slowed down by the process variation.
The effect of the process variation on different chip timings is usually in a normal distribution (an average value being μglobal, and a variance being σglobal), the fastest and the slowest process corners are usually defined according to a multiple of σglobal (such as 3 times or 6 times of σ) or performance statistical data obtained by means of segmentation test. For the segmentation test, the process parameters (doping concentration, oxidation layer thickness, etc.) are artificially set to be close to manufacturing the slowest or the fastest chip. Apart from the fastest and the slowest process corners, some crossing process corners, for example, consist of a fastest p channel transistor (p-FET) and a slowest n channel transistor (n-FET) or vice versa. Generally, a process base provides five process corners, that is, FF, FNSP, TT, SNFP and SS. FF represents that the circuit consists of a fastest p-FET and a fastest n-FET; TT represents that the circuit consists of a typical p-FET and a typical n-FET; SS represents that the circuit consists of a slowest p-FET and a slowest n-FET; FNSP and SNFP are crossing process corners, and FNSP represents that the circuit consists of a slowest p-FET and a fastest n-FET; and SNFP represents that the circuit consists of a fastest p-FET and a slowest n-FET. Generally, the crossing process corner is more critical in an analogue circuit, but secondary in a digital circuit.
The local variation is increasing as a CMOS process size is scaling. Scaling of a transistor size may cause a standard deviation σVT of a threshold voltage and a current factor σk/k (k=μCOXW/L) to increase because they are proportional to the square root of the reciprocal of the area of an active region.
The effect of the local variation on a path delay may be described by n same logic gates with inversion time (rising or falling time) being tgate and a corresponding standard deviation being a σt,gate. The path delay td=n×tgate increases linearly with n, but the standard deviation σt,d is proportional to the square root of n, and therefore, a relative deviation σt,d/td of the path delay is proportional to the square root of the reciprocal of n. Therefore, an absolute deviation of the path delay increases as the path increases, but the relative deviation decreases as the path increases.
With the evolution of the process, the effect of the process variation on the chip timing is increasingly severely under an advanced process. After fabricating the manufacture of the chip, each chip may in a different process corner, and the specific process corner of the chip cannot be learnt without corresponding process corner detection means. A ring oscillator is a most commonly used structure for detecting a process corner, and the principle thereof is to count the number of oscillations of the ring oscillator within a certain period, and when the process corner of the chip is relatively good, the time delay of the device is relatively small, and the number of oscillations of the ring oscillator within the same period is relatively large; and when the process corner of the chip is not good, the number of oscillations is relatively small, and therefore, a counting result of the number of the oscillations may reflect the process corner of the chip.
A logical structure generally adopted by a traditional ring oscillator is a ring formed by connecting an odd number of inverters end-to-end, and generates an oscillation waveform by using the time delay of the inverters and inverse functions thereof. The change of the process corner of the ring oscillator based on an inverter chain may change its oscillation frequency, but changes of the voltage and temperature may also affect the oscillation frequency. Although the effect of voltage fluctuations can be eliminated by using LDO supplying power to the circuit with stable and accurate voltage, the effect of temperature fluctuations on the ring oscillator cannot be eliminated. It can be found by HSPICE simulation that, in different process corners, there are overlaps in the counting result of the ring oscillator, that is, under two process corners, when a worse process corner is in a low temperature while a better process corner is in a high temperature condition, the counting range overlaps, thus, the process corner of the chip cannot be correctly distinguished by the counting result.